LG Optimus 2X and NVIDIA Tegra 2 review, complete with a discussion of the 2011 SoC space, did TI announce its OMAP 5 SoC.
OMAP 5 will go into production in the second half of 2011 and ship in phones during the second half of 2012. It’s a 28nm SoC with significant architectural upgrades compared to the OMAP 4.
While the OMAP 4 integrates a pair of ARM Cortex A9 cores, OMAP 5 features two ARM Cortex A15 cores. TI already announced that it was ARM’s first licensee of the Cortex A15, so the OMAP 5 announcement is not too surprising.
The ARM Cortex A15 cores can run at speeds of up to 2GHz, although specific frequencies will depend on the OEM implementation. At 2GHz TI claims the pair of Cortex A15s should be 3x the speed of the 1GHz Cortex A9s in the OMAP 4330. At the same clock speed, TI is boasting a 50% performance advantage from the A15 over the A9.
With the OMAP 3 TI had a 256KB L2 used by its single Cortex A8. The OMAP 4 quadrupled L2 cache size to 1MB and shared it among both of its Cortex A9s. TI’s OMAP 5 doubles L2 cache size to 2MB, operating at the CPU clock speed, and it’s once again shared by the SoC’s two CPU cores (in this case Cortex A15s). The OMAP 5 retains the same dual-channel LPDDR2 memory interface from the OMAP 4.
Architecturally we still don’t know much about what makes up a Cortex A15, although I suspect we’ll get more of that in the coming months. Update: It looks like ARM has released some info on the A15. It appears to be a wider, deeper, even more OoO architecture. More on this later.
In our Tegra 2 review I mentioned that the transition from ARM11, to Cortex A8 and now to Cortex A9 left us with a generational performance improvement each step of the way. The move to A15 will be no different. ARM’s Cortex A8 went mainstream in the performance segment in 2010, Cortex A9 will do the same in 2011 and with any luck we’ll see A15 before the end of 2012. It’s this sort of yearly cadence that ARM and its partners must keep up in order to really catch up and surpass what Intel has been promising with Atom. Atom came out in 2008 and it won’t be until late 2012 that its architecture is truly refreshed. For a company that survived the mistakes of NetBurst, Intel doesn’t seem to have learned much of a lesson there.
In addition to its dual Cortex A15 CPUs, the OMAP 5 will feature two ARM Cortex M4 cores as well. The M4 isn’t very useful as a general purpose microprocessor, it only supports the ARM Thumb/Thumb-2 instruction sets (not the full 32-bit ARMv7-A ISA). The M4 does have a suite of signal processing extensions that can be used to accelerate audio/video encode and decode. One application of the M4s will be still picture enhancement. A goal for the next-generation of SoCs is to begin to bridge the gap between smartphone camera quality and high-end point-and-shoot and DSLR cameras. Obviously we’ll always be bound by the poor optics possible on smartphones, however there’s still a lot that can be done in hardware to improve the quality of what’s captured.
The OMAP 5 supports up to four cameras. One demo I saw Intel put together a while ago was of a smartphone with two equal resolution/quality cameras on its back. The only difference between the two was the focal length of the lens. Whenever you took a photo with the demo camera you’d actually capture the scene at two (vastly) different focal lengths. The SoC (in this case an Atom) would use the captured data to produce one image where the entire scene was in focus, with improved sharpness/detail over a single camera solution. It’s possible that OMAP 5 based smartphones may feature similar technologies and use its Cortex M4s to merge/interpolate data from the camera sensors.
As ARM’s CPUs grow in power consumption, the amount of fixed function or specialized silicon set aside to offload various tasks will increase. The Cortex A15s should be used only for those applications that absolutely need them, anything else should be offloaded.
The OMAP 5 SoC integrates Imagination Technologies’ PowerVR SGX 544 GPU, although it’s unclear how many cores will be present in TI’s implementation. Each SGX 544 core has four USSE2 pipes compared to four USSE pipes in the SGX 540, and two USSE pipes in the SGX 530. Each USSE2 pipe offers an increase in compute power compared to the old USSE pipes, however I don’t have details on specific differences in internal organization.
TI announced two versions of the OMAP 5: the 5430 and 5432. The OMAP 5430 features a 14 x 14mm PoP with LPDDR2 memory support, while the 5432 is a larger 17 x 17mm BGA package with DDR3/DDR3L support. The 5430 will likely be used in smartphones while the 5432’s larger size would be better suited for tablets.