Intel & Micron Announce First 20nm MLC NAND Flash for Use in SSDs

We just started testing SSDs based on IMFT 25nm NAND Flash and look at what Intel/Micron just announced? The first 8GB MLC NAND device built on a 20nm process. This is obviously an announcement of pre-production silicon, it’ll take IMFT until the second half of this year (at least) to start shipping production quality 20nm NAND.

At 50nm IMFT NAND was good for 10,000 program/erase cycles (rated, not actual). The move to 34nm dropped that to 3000 - 5000 program erase cycles, a value that was maintained with the move to 25nm. I asked Micron how long NAND will last at 20nm and was told that p/e cycles are comparable to where 25nm was at a similar point in its development cycle. Micron expects quality to ramp over time and ultimately hit a similar point to existing 25nm NAND, which is good for controller manufacturers as it means any ECC/NAND redundancy efforts they have already implemented should support the new 20nm product.

An 8GB 2-bit-per-cell MLC NAND device built at 20nm has a die area of 118mm2, down from 167mm2 at 25nm. A single 8GB NAND device wasn’t built at 34nm.



IMFT is on a 15 - 18 month process cadence, meaning this transition was of course planned for in advance. The first 20nm NAND is being manufactured at the IMFT Fab in Lehi, Utah, which is currently producing 25nm NAND. Some equipment upgrades are necessary to support 20nm. IMFT will also transition its fabs in Manassas, VA and Singapore to 20nm at a later point.

For consumers there’s an obvious win. We need smaller transistor geometries to reduce the cost of NAND, which ultimately reduces the cost of SSDs. The days of 50% annual price reductions are over however, expect to see a conservative 20 - 30% drop in price for SSDs that use 20nm NAND over 25nm NAND.